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| intelligent temperature monitor and dual pwm fan controller adm1031 ?2008 scillc. all rights reserved. publication order number: january 2008 C rev. 3 adm1031/d features optimized for pentium? iii reduced guardbanding software automatic fan speed control, independent of cpu intervention after initial setup control loop to minimal acoustic noise and battery consumption remote temperature measurement accurate to 1c using remote diode (two channels) 0.125c resolution on external temperature channels local sensor with 0.25c resolution pulse width modulation (pwm) fan control for two fans programmable pwm frequency and pwm duty cycle tach fan speed measurement (two channels) analog input to measure fan speed of 2-wire fans (using sense resistor) 2-wire system management bus (smbus) with ara support overtemperature therm output pin for cpu throttling programmable int output pin configurable offsets for temperature channels 3 v to 5.5 v supply range shutdown mode to mini mize power consumption limit comparison of all monitored values applications notebook pcs, network servers, and personal computers telecommunications equipment general description the adm1031 is an acpi-compliant, three-channel digital thermometer and under/over temperature alarm for use in personal computers and thermal management systems. optimized for the pentium iii, the part offers a 1 c higher accuracy, which allows system designers to safely reduce temperature guardbanding and increase system performance. two pwm fan control outputs control the speed of two cooling fans by varying output duty cycle. duty cycle values between 33% and 100% allow smooth control of the fans. the speed of each fan can be monitored via tach inputs, which can be reprogrammed as analog inputs to allow speeds for 2-wire fans to be measured via sense resistors. the device also detects a stalled fan. a dedicated fan speed control loop provides control without the intervention of cpu software. it also ensures that if the cpu or system locks up, each fan can still be controlled based on temperature measurements, and the fan speed is adjusted to correct any changes in system temperature. fan speed can also be controlled using existing acpi software. two inputs (four pins) are dedicated to remote temperature- sensing diodes with an accuracy of 1 c, and an on-chip temperature sensor allows ambient temperature to be monitored. the device has a programmable int output to indicate error conditions, and a dedicated fan_fault output to signal fan failure. the therm pin is a fail-safe output for overtemperature conditions that can be used to throttle a cpu clock. functional block diagram slave address register serial bus interface address pointer register interrupt status registers value and limit registers offset registers configuration registers limit comparator fan filter register fan characteristics register add sda scl gnd adm1031 int (smbalert) therm fan_fault pwm_out1 d1+ d1? v cc adc fan speed config register fan speed counter analog multiplexer pwm controllers tach signal conditioning bandgap temperature sensor 2.5v bandgap reference t ach2/ain2 t ach1/ain1 pwm_out2 d2+ d2? 1 3 4 2 9 10 12 11 6 13 15 16 14 7 8 5 02402-001 figure 1.
adm1031 rev. 3 | page 2 of 35 | www.onsemi.com table of contents features...............................................................................................1 applications .......................................................................................1 general description..........................................................................1 functional block diagram...............................................................1 specifications .....................................................................................3 absolute maximum ratings ............................................................5 thermal resistance.......................................................................5 esd caution ..................................................................................5 pin configuration and function descriptions .............................6 typical performance characteristics..............................................7 functional description.....................................................................9 internal registers ..........................................................................9 serial bus interface .....................................................................10 alert response address .............................................................12 temperature measurement system ..............................................13 internal measurement ................................................................13 external measurement ...............................................................13 layout considerations ...............................................................15 addressing the device................................................................15 the interrupt system..................................................................15 using therm as an input ........................................................16 status registers............................................................................16 fan control modes of operation .................................................17 automatic fan speed control...................................................17 filtered control mode................................................................21 pwm duty cycle select mode .................................................24 rpm feedback mode .................................................................24 fan drive and speed measurement..............................................26 fan speed measurement equations .........................................26 fan drive using pwm control ................................................26 fan speed measurement ............................................................27 fan faults .....................................................................................27 outline dimensions........................................................................35 ordering guide ...............................................................................35 revision history 01/08 - rev 3: conversion to on semiconductor 9/05rev. a to rev. b updated format ................................................................. universal changes to ordering guide...........................................................33 4/03rev. 0 to rev. a added esd caution ......................................................................... 3 updated outline dimensions .......................................................30 adm1031 rev. 3 | page 3 of 35 | www.onsemi.com specifications t a = t min to t max , v cc = v min to v max , unless otherwise noted. 1 table 1. parameter min typ max unit test conditions/comments power supply supply voltage, v cc 3.0 3.30 5.5 v supply current, i cc 1.4 3 ma interface inactive, adc active 32 50 a standby mode temperature-to-digital converter local sensor accuracy 1 3 c resolution 0.25 c remote diode1 sensor accuracy 0.5 1 c 60c t d 100c remote diode2 sensor accuracy 0.5 1.75 c 60c t d 100c resolution 0.125 c remote sensor source current 180 a high level 11 a low level open-drain digital outputs ( therm , int , fan_fault , pwm_out) output low voltage, v ol 0.4 v i out = C6.0 ma; v cc = 3 v high-level output leakage current, i oh 0.1 1 a v out = v cc ; v cc = 3 v open-drain serial data bus output (sda) output low voltage, v ol 0.4 v i out = C6.0 ma; v cc = 3 v high-level output leakage current, i oh 0.1 1 a v out = v cc serial bus digital inputs (scl, sda) input high voltage, v ih 2.1 v input low voltage, v il 0.8 v hysteresis 500 mv digital input logic levels 2 (add, therm , tach1/2) input high voltage, v ih 2.1 v input low voltage, v il 0.8 v digital input leakage current input high current, i ih C1 a v in = v cc input low current, i il 1 a v in = 0 input capacitance, c in 5 pf fan rpm-to-digital converter accuracy 6 % 60c t a 100c full-scale count 255 tach nominal input rpm 4400 rpm divisor n = 1, fan count = 153 2200 rpm divisor n = 2, fan count = 153 1100 rpm divisor n = 4, fan count = 153 550 rpm divisor n = 8, fan count = 153 conversion cycle time 637 ms adm1031 rev. 3 | page 4 of 35 | www.onsemi.com parameter min typ max unit test conditions/comments serial bus timing 3 clock frequency, f sclk 10 100 khz see figure 2 glitch immunity, t sw 50 ns see figure 2 bus free time, t buf 4.7 s see figure 2 start setup time, t su;sta 4.7 s see figure 2 start hold time, t hd ; sta 4 s see figure 2 stop condition setup time, t su;sto 4 s see figure 2 scl low time, t low 1.3 s see figure 2 scl high time, t high 4 50 s see figure 2 scl, sda rise time, t r 1000 ns see figure 2 scl, sda fall time, t f 300 ns see figure 2 data setup time, t su;dat 250 ns see figure 2 data hold time, t hd;dat 300 ns see figure 2 1 typicals are at t a = 25c and represent most likely parametric norm. shutdown current typ is measured with v cc = 3.3 v. 2 add is a three-state input that can be pulled high, low, or left open-circuit. 3 timing specifications are tested at logic levels of v il = 0.8 v for a falling edge and v ih = 2.2 v for a rising edge. adm1031 rev. 3 | page 5 of 35 | www.onsemi.com absolute maximum ratings table 2. parameter rating positive supply voltage (v cc ) 6.5 v voltage on any input or output pin C0.3 v to +6.5 v input current at any pin 5 ma package input current 20 ma maximum junction temperature ( t jmax ) 150c storage temperature range C65c to +150c lead temperature, soldering vapor phase 60 sec 215c infrared 15 sec 200c esd rating all pins 2000 v stresses above those listed under absolute maximum ratings can cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods can affect device reliability. thermal resistance ja is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. table 3. thermal resistance package type ja jc unit 16-lead qsop package 105 39 c/w p s t low t r t f t hd:sta t hd:dat t su:dat t su:sta t hd:sta t su:sto t high scl ps sd a t buf 02402-002 figure 2. diagram for serial bus timing esd caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although this product features proprietary esd protection circuitry, permanent dama ge can occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. adm1031 rev. 3 | page 6 of 35 | www.onsemi.com pin configuration and function descriptions 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 tach1/ain1 pwm_out2 tach2/ain2 therm v cc gnd pwm_out1 sda int(smbalert) add d1+ fan_fault d1? d2? d2+ scl top view (not to scale) adm1031 02402-003 figure 3. pin configuration table 4. pin function descriptions pin no. mnemonic description 1 pwm_out1 digital output, open-drain. pulse width modulated output to control fan speed. requires pull-up resistor (10 k typical). 2 tach1/ain1 digital/analog input. fan tachometer input to measure fan1 fan speed. can be reprogrammed as an analog input to measure speed of a 2-wire fan via a sense resistor (2 typical). 3 pwm_out2 digital output, open-drain. pulse width modulated output to control fan2 fan speed. requires pull-up resistor (10 k typical). 4 tach2/ain2 digital/analog input. fan tachometer input to measure fan2 fan speed. can be reprogrammed as an analog input to measure speed of a 2-wire fan via a sense resistor (2 typical). 5 gnd system ground. 6 v cc power. can be powered by 3.3 v standby power if monitoring in low power states is required. 7 therm digital i/o, open-drain. an active low thermal overload output that indicates a violation of a temperature set point (overtemperature). also acts as an input to provid e external fan control. when this pin is pulled low by an external signal, a status bit is set, and the fan speed is set to full-on. requires pull-up resistor (10 k). 8 fan_fault digital output, open-drain. can be used to signal a fan fa ult. drives second fan to fu ll speed if one fan fails. requires pull-up resistor (typically 10 k). 9 d1C analog input. connected to cathode of first re mote temperature-sensing diode. the temperature-sensing element is either a pentium iii substrate transistor or a general-purpose 2n3904. 10 d1+ analog input. connected to anode of first remote temperature-sensing diode. 11 d2C analog input. connected to cathode of second remote temperature-sensing diode. 12 d2+ analog input. connected to anode of second remote temperature-sensing diode. 13 add three-state logic input. sets tw o lower bits of device smbus address. 14 int ( smbalert ) digital output, open-drain. can be programmed as an interrupt (smbus alert) output for temperature/fan speed interrupts. requires pull-up resistor (10 k typical). 15 sda digital i/o, serial bus bidirectional data. open-drain output. requires pull-up resistor (2.2 k typical). 16 scl digital input, serial bus clock. requires pull-up resistor (2.2 k typical). adm1031 rev. 3 | page 7 of 35 | www.onsemi.com typical performance characteristics 15 ?20 1 100 leakage resistance (m ) remote temperature error ( c) 10 5 0 ?5 ?10 ?15 3.3 10 30 dxp to gnd dxp to v cc (3.3v) 02402-004 figure 4. temperature error vs. pcb track resistance 17 ?1 0 frequency (hz) remote temperature error ( c) 15 13 11 9 7 5 3 1 500k 2m 4m 6m 10m 100m 400m v in = 200mv p-p v in = 100mv p-p 02402-005 figure 5. temperature error vs. power supply noise frequency 7 ?1 0 frequency (hz) remote temperature error ( c) 100k 1m 100m 200m 300m 400m 500m 6 5 4 3 2 1 0 v in = 40mv p-p v in = 20mv p-p 02402-006 figure 6. temperature error vs. common-mode noise frequency 110 0 0 110 piii temperature ( c) reading ( c) 100 90 80 70 60 50 40 30 20 10 10 20 30 40 50 60 70 80 90 100 02402-007 figure 7. pentium iii temperature measurement vs. adm1031 reading 1 ?16 147 dxp, dxn capacitance (nf) remote temperature error ( c) 0 ?1 ?2 ?3 ?4 ?5 ?6 ?7 ?8 ?9 ?10 ?11 ?12 ?13 ?14 ?15 2.2 3.3 4.7 10 22 02402-008 figure 8. temperature error vs. capacitance between d+ and dC 110 0 0 sclk frequency (khz) supply current ( a) 1000 100 90 80 70 60 50 40 30 20 10 1 5 10 25 50 75 100 250 500 750 v cc = 5v v cc = 3.3v 02402-009 figure 9. standby current vs. clock frequency adm1031 rev. 3 | page 8 of 35 | www.onsemi.com 7 ?1 0 frequency (hz) remote temperature error ( c) 100k 1m 100m 200m 300m 400m 500m 6 5 4 3 2 1 0 v in = 30mv p-p v in = 20mv p-p 02402-010 figure 10. temperature error vs. differential-mode noise frequency 200 ?20 0 supply voltage (v) supply current ( a) 180 160 140 120 100 80 60 40 20 0 1.1 1.3 1.5 1.7 1.9 2.1 2.5 2.9 4.5 add = v cc add = gnd add = hi-z 02402-011 figure 11. standby supply current vs. supply voltage 0.08 ??0.80 0 temperature ( c) error ( c) 0 ?0.08 ?0.16 ?0.24 ?0.32 ?0.40 ?0.48 ?0.56 ?0.64 ?0.72 20 40 60 80 85 100 105 120 02402-012 . figure 12. local sensor temperature error 0.08 ??0.80 0 temperature ( c) error ( c) 0 ?0.08 ?0.16 ?0.24 ?0.32 ?0.40 ?0.48 ?0.56 ?0.64 ?0.72 20 40 60 80 85 100 105 120 02402-013 figure 13. remote temp erature sensor error 1.30 0.80 2.0 supply voltage (v) supply current (ma) 5.0 1.25 1.20 1.15 1.10 1.05 1.00 0.95 0.90 0.85 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 02402-014 figure 14. supply current vs. supply voltage 120 0 0 time (sec) temperature ( c) 10 110 100 90 80 70 60 50 40 30 20 10 123456789 02402-015 figure 15. response to thermal shock adm1031 rev. 3 | page 9 of 35 | www.onsemi.com functional description the adm1031 is a temperature monitor and dual pwm fan controller for microprocessor-based systems. the device communicates with the system via a serial system management bus (smbus). the serial bus controller has a hardwired address pin for device selection (pin 13), a serial data line for reading and writing addresses and data (pin 15), and an input line for the serial clock (pin 16). all control and programming functions of the adm1031 are perf ormed over the serial bus. the device also supports alert response address (ara). internal registers brief descriptions of the adm1031s principal internal registers are given below. for more detailed information on the function of each register, see adm1031 rev. 3 | page 10 of 35 | www.onsemi.com table 18 through table 33. configuration register this register controls and configures various functions on the device. address pointer register this register contains the address that selects one of the other internal registers. when writin g to the adm1031, the first byte of data is always a register address, which is written to the address pointer register. status registers these registers provide status of each limit comparison. value and limit registers theses registers store the results of temperature and fan speed measurements, along with their limit values. fan speed configuration register this register is used to program the pwm duty cycle for each fan. offset registers these registers allow the temperature channel readings to be offset by a 5-bit twos complement value written to these registers. these values are automatically added to the temperature values (or subtracted from if negative). this allows the systems designer to optimize the system if required, by adding or subtracting up to 15c from a temperature reading. fan characteristics registers these registers are used to select the spin-up time, pwm frequency, and speed range for the fans used. therm limit registers these registers contain the temperature values at which therm is asserted. t min /t range registers these registers are read/write registers that hold the minimum temperature value below which the fan does not run when the device is in automatic fan speed control mode. these registers also hold the temperature range value that defines the range over which auto fan control is provided, and hence determines the temperature at which the fan is run at full speed. serial bus interface control of the adm1031 is carried out via the smbus. the adm1031 is connected to this bus as a slave device, under the control of a master device, for example, the 810 chipset. the adm1031 has a 7-bit serial bu s address. when the device is powered up, it does so with a default serial bus address. the five msbs of the address are set to 01011; the two lsbs are determined by the logical state of pin 13 (add). this is a three- state input that can be grounded, connected to v cc , or left open-circuit to give three different addresses. the state of the add pin is only sampled at power-up, so changing add with power on has no effect until the device is powered off, then on again. table 5. add pin truth table add pin a1 a0 gnd 0 0 no connect 1 0 v cc 0 1 if add is left open-circuit, then the default address is 0101110. the facility to make hardwired changes at the add pin allows the user to avoid conflicts with other devices sharing the same serial bus; for example, if more than one adm1031 is used in a system. serial bus protocol 1. the master initiates data transfer by establishing a start condition, defined as a high-to-low transition on the serial data line sda while the serial clock line scl remains high. this indicates that an address/data stream follows. all slave peripherals connected to the serial bus respond to the start condition, and shift in the next eight bits, consisting of a 7-bit address (msb first) plus an r/ w bit that determines the direction of the data transfer, that is, whether data is written to or read from the slave device. the peripheral whose address corresponds to the transmitted address responds by pulling the data line low during the low period before the ninth clock pulse, known as the acknowledge bit. all other devices on the bus now remain idle while the selected device waits for data to be read from or written to it. if the r/ w bit is a 0, then the master writes to the slave device. if the r/ w bit is a 1, then the master reads from the slave device. 2. data is sent over the serial bus in sequences of nine clock pulses, eight bits of data, followed by an acknowledge bit from the slave device. transitions on the data line must occur during the low period of the clock signal and remain stable during the high period, as a low-to-high transition when the clock is high can be interpreted as a stop signal. the number of data bytes that can be transmitted over the serial bus in a single read or write operation is limited only by what the master and slave devices can handle. 3. when all data bytes have been read or written, stop conditions are established. in write mode, the master pulls adm1031 rev. 3 | page 11 of 35 | www.onsemi.com the data line high during the tenth clock pulse to assert a stop condition. in read mode, the master device overrides the acknowledge bit by pulling the data line high during the low period before the ninth clock pulse. this is known as no acknowledge. the master then takes the data line low during the low period before the tenth clock pulse, then high during the tenth clock pulse to assert a stop condition. any number of bytes of data can be transferred over the serial bus in one operation, but it is not possible to mix read and write in one operation, because the type of operation is determined at the beginning and cannot subsequently be changed without starting a new operation. in the case of the adm1031, wr ite operations contain either one byte or two bytes, and read operations contain one byte, and perform the functions described next. writing data to a register to write data to one of the device data registers or read data from it, the address pointer register must be set so that the correct data register is addressed; data can then be written to that register or read from it. th e first byte of a write operation always contains an address that is stored in the address pointer register. if data is to be written to the device, the write operation contains a second data byte that is written to the register selected by the address pointer register. this is illustrated in figure 16. the device address is sent over the bus followed by r/ w set to 0. this is followed by two data bytes. the first data byte is the address of the internal data register to be written to, which is stored in the address pointer register. the second data byte is the data to be written to the internal data register. reading data from a register when reading data from a register there are two possibilities: 1. if the adm1031s address pointer register value is unknown or not the desired value, it is first necessary to set it to the correct value before data can be read from the desired data register. this is done by performing a write to the adm1031 as before, but only the data byte containing the register address is sent, as data is not to be written to the register. this is shown in figure 17. a read operation is then performed consisting of the serial bus address, r/ w bit set to 1, followed by the data byte read from the data register. this is shown in figure 18. 2. if the address pointer register is known to be already at the desired address, data can be read from the corresponding data register without first writing to the address pointer register, so figure 17 can be omitted. notes ? although it is possible to read a data byte from a data register without first writing to the address pointer register, if the address pointer register is already at the correct value, it is not possible to write data to a register without writing to the address pointer register. this is because the first data byte of a write is always written to the address pointer register. ? in figure 16, figure 17, and figure 18, the serial bus address is shown as the default value 01011(a1)(a0), where a1 and a0 are set by the three-state add pin. ? the adm1031 also supports the read byte protocol, as described in the system management bus specification. adm1031 rev. 3 | page 12 of 35 | www.onsemi.com start by master stop by master ack. by adm1031 ack. by adm1031 ack. by adm1031 0 119 9 1 0 1 1 a1 a0 r/w d7 d6 d5 d4 d3 d2 d1 d0 scl sda frame 1 serial bus address byte frame 2 address pointer register byte frame 3 data byte sda (continued) scl (continued) 9 1 d7 d6 d5 d4 d3 d2 d1 d0 02402-016 figure 16. writing a register address to the address pointer register, then writing data to the selected register stop by master ack. by adm1031 ack. by adm1031 start by master scl 119 9 frame 1 serial bus address byte frame 2 address pointer register byte 0 1 0 1 1 a1 a0 r/w d7 d6 d5 d4 d3 d2 d1 d0 sda 02402-017 figure 17. writing to the address pointer register only stop by master ack. by adm1031 no ack. by master start by master scl 119 9 frame 1 serial bus address byte frame 2 data byte from adm1031 0 1 0 1 1 a1 a0 r/w d7 d6 d5 d4 d3 d2 d1 d0 sda 02402-018 figure 18. reading data from a previously selected register alert response address alert response address (ara) is a feature of smbus devices that allows an interrupting device to identify itself to the host when multiple devices exist on the same bus. the int output can be used as an interrupt output or can be used as an smbalert . one or more int outputs can be connected to a common smbalert line connected to the master. if a devices int line goes low, the following procedure occurs: 1. smbalert is pulled low. 2. master initiates a read operation and sends the alert response address (ara = 0001 100). this is a general call address that must not be used as a specific device address. 3. the device whose int output is low responds to the alert response address, and the master reads its device address. the address of the device is now known and can be interrogated in the usual way. 4. if more than one devices int output is low, the one with the lowest device address has priority, in accordance with normal smbus arbitration. 5. once the adm1031 has responded to the alert response address, it resets its int output. however, if the error condition that caused the interrupt persists, then int is reasserted on the next monitoring cycle. adm1031 rev. 3 | page 13 of 35 | www.onsemi.com temperature measurement system internal measurement the adm1031 contains an on-chip bandgap temperature sensor. the on-chip adc performs conversions on the output of this sensor and outputs the temperature data in 10-bit twos com- plement format. the resolution of the local temperature sensor is 0.25c. the format of the temperature data is shown in table 6. external measurement the adm1031 can measure the temp eratures of two external diode sensors or diode-connected transistors, connected to pins 9 and 10, and pins 11 and 12. these pins are dedicated temperature input channels. the function of pin 7 is as a therm input/output and is used to flag overtemperature conditions. the forward voltage of a diode or diode-connected transistor, operated at a constant current, exhibits a negative temperature coefficient of about C2 mv/c. unfortunately, the absolute value of v be , varies from device to device, and individual calibration is required to null this out. as a result, the technique is unsuitable for mass production. the technique used in the adm 1031 is to measure the change in v be when the device is operated at two different currents. this is given by vbe = kt/q ln (n) where: k is boltzmanns constant. q is charge on the carrier. t is absolute temperature in kelvins. n is ratio of the two currents. figure 19 shows the input signal conditioning used to measure the output of an external temperature sensor. this figure shows the external sensor as a substrate transistor, provided for temperature monitoring on some microprocessors, but it could equally well be a discrete transistor. remote sensing transistor bias diode d+ d? to adc low-pass filter f c = 65khz v dd v out+ v out? i bias in i 02402-019 figure 19. signal conditioning if a discrete transistor is used, then the collector is not grounded, and is linked to the base. if a pnp transistor is used, the base is connected to the dC input and the emitter to the d+ input. if an npn transistor is used, the emitter is connected to the dC input and the base to the d+ input. one lsb of the adc correspond s to 0.125c, so the adm1031 can theoretically measure temperatures from C127c to +127.75c, although C127c is outside the operating range for the device. the extended temperature resolution data format is shown in table 7 and adm1031 rev. 3 | page 14 of 35 | www.onsemi.com table 8. table 6. temperature data format (local temperature and remote temperature high bytes) temperature (c) digital output C128c 1000 0000 C125c 1000 0011 C100c 1001 1100 C75c 1011 0101 C50c 1100 1110 C25c 1110 0111 C1c 1111 1111 0c 0000 0000 +1c 0000 0001 +10c 0000 1010 +25c 0001 1001 +50c 0011 0010 +75c 0100 1011 +100c 0110 0100 +125c 0111 1101 +127c 0111 1111 table 7. remote sensor extended temperature resolution extended resolution (c) remote temperature low bits 0.000 000 0.125 001 0.250 010 0.375 011 0.500 100 0.625 101 0.750 110 0.875 111 the extended temperature resolution for the local and remote channels is stored in the extended temperature resolution register (register 006), and is outlined in table 31. adm1031 rev. 3 | page 15 of 35 | www.onsemi.com table 8. local sensor extended temperature resolution extended resolution (c) local temperature low bits 0.00 00 0. 25 01 0.50 10 0.75 11 to prevent ground noise interfering with the measurement, the more negative terminal of the sensor is not referenced to ground, but biased above ground by an internal diode at the dC input. if the sensor is used in a very noisy environment, a capacitor of value up to 1000 pf can be placed between the d+ and dC inputs to filter the noise. to m e a sure v | , the sensor is switched between operating currents of i and n i. the resulting waveform is passed through a 65 khz low-pass filter to remove noise, then to a chopper-stabilized amplifier that performs the functions of amplification and rectification of the waveform to produce a dc voltage proportional to v be . this voltage is measured by the adc to give a temperature output in 11-bit twos complement format. to further reduce the effects of noise, digital filtering is performed by averaging the results of 16 measurement cycles. an external temperature measurement nominally takes 9.6 ms. layout considerations digital boards can be electrically noisy environments and care must be taken to protect the analog inputs from noise, particularly when measuring the very small voltages from a remote diode sensor. the following precautions should be taken: 1. place the adm1031 as close as possible to the remote sensing diode. provided that the worst noise sources such as clock generators, data/address buses, and crts are avoided, this distance can be 4 to 8 inches. 2. route the d+ and dC tracks close together, in parallel, with grounded guard tracks on each side. provide a ground plane under the tracks if possible. 3. use wide tracks to minimize inductance and reduce noise pickup. ten mil track minimum width and spacing is recommended. 10mil 10mil 10mil 10mil 10mil 10mil 10mil gnd d+ gnd d? 02402-020 figure 20. arrangement of signal tracks 4. try to minimize the number of copper/solder joints, which can cause thermocouple effects. where copper/solder joints are used, make sure that they are in both the d+ and dC path and at the same temperature. thermocouple effects should not be a major problem as 1c corresponds to about 200 v, and thermocouple voltages are about 3 v/c of temperature difference. unless there are two thermocouples with a big temperature differential between them, thermocouple voltages sh ould be much less than 200 v. 5. place a 0.1 f bypass capacitor close to the adm1031. 6. if the distance to the remote sensor is more than 8 inches, the use of twisted pair cable is recommended. this works up to about 6 to 12 feet. 7. for extra long distances (up to 100 feet), use a shielded twisted pair cable, such as the belden #8451 microphone cable. connect the twisted pair to d+ and dC and the shield to gnd close to th e adm1031. leave the remote end of the shield unconnected to avoid ground loops. because the measurement technique uses switched current sources, excessive cable and/or filter capacitance can affect the measurement. when using long cables, the filter capacitor c1 can be reduced or removed. in any case the total shunt capacitance should not exceed 1000 pf. cable resistance can also introduce errors. one ohm series resistance introduces about 0.5c error. addressing the device add (pin 13) is a three-state input. it is sampled, on power-up to set the lowest two bits of the serial bus address. up to three addresses are available to the systems designer via this address pin. this reduces the likelihood of conflicts with other devices attached to the system management bus. the interrupt system the adm1031 has two interrupt outputs, int and therm . these have different functions. int responds to violations of software programmed temperature limits and is maskable. therm is intended as a fail-safe interrupt output that cannot be masked. if the temperature is below the low temperature limit, the int pin is asserted low to indicate an out-of-limit condition. if the temperature exceeds the high temperature limit, the int pin is also asserted low. a third limit, therm limit, can be programmed into the device to set the temperature limit above which the overtemperature therm pin is asserted low. the behavior of the high limit and therm limit is as follows: 1. whenever the temperature measured exceeds the high temperature limit, the int pin is asserted low. 2. if the temperature exceeds the therm limit, the therm output asserts low. this can be used to throttle the cpu clock. if the therm -to-fan enable bit (bit 7 of therm adm1031 rev. 3 | page 16 of 35 | www.onsemi.com behavior/revision register) is cleared to 0, then the fans do not run full-speed. the therm limit can be programmed at a lower temperature than the high temperature limit. this allows the system to run in silent mode, where the cpu can be throttled while the cooling fan is off. if the temperature continues to increase, and exceeds the high temperature limit, an int is generated. software can then decide whether the fan should run to cool the cpu. this allows the system to run in silent mode. 3. if the therm -to-fan enable bit is set to 1, then the fan runs full-speed whenever therm is asserted low. in this case, both throttling and active cooling take place. if the high temperature limit is programmed to a lower value than the therm limit, exceeding the high temperature limit asserts int low. software could change the speed of the fan depending on temperature readings. if the temperature continues to increase and exceeds the therm limit, therm asserts low to throttle the cpu and the fan runs full-speed. this allows the system to run in performance mode, where active cooling takes place and the cpu is only throttled at high temperature. using the high temperature limit and the therm limit in this way allows the user to gain maximum performance from the system by only slowing it down, should it be at a critical temperature. although the adm1031 does not have a dedicated interrupt mask register, clearing the appropriate enable bits in configuration register 2 clears the appropriate interrupts and masks out future interrupts on that channel. disabling interrupt bits prevents out-of-limit conditions from generating an interrupt or setting a bit in the status registers. using therm as an input the therm pin is an open-drain input/output pin. when used as an output, it signals overtemperature conditions. when asserted low as an output, the fan is driven full-speed if the therm -to-fan enable bit is set to 1 (bit 7 of register 03f). when therm is pulled low as an input, the therm bit (bit 7) of status register 2 is set to 1, and the fans are driven full-speed. note that the therm -to-fan enable bit has no effect whenever therm is used as an input. if therm is pulled low as an input, and the therm -to-fan enable bit = 0, then the fans are still driven full-speed. the therm -to-fan enable bit only affects the behavior of therm when used as an output. status registers all out-of-limit conditions are flagged by status bits in status register 1 (002) and status register 2 (003). bit 0 (alarm speed) and bit 1 (fan fault) of status register 1, once set, can be cleared by reading status register 1. once the alarm speed bit is cleared, this bit is not reasserted on the next monitoring cycle even if the condition still persists. this bit can be reasserted only if the fan is no longer at alarm speed. bit 1 (fan fault) is set whenever a fan tach failure is detected. once cleared, it reasserts on subsequent fan tach failures. bit 2 and bit 3 of status register 1 and status register 2 are the remote 1 and remote 2 temperature high and low status bits. exceeding the high or low temperature limits for the external channel sets these status bits. reading the status register clears these bits. however, these bits are reasserted if the out-of-limit condition still exists on the next monitoring cycle. bit 6 and bit 7 are the local temperature high and low status bits. these behave exactly the same as the remote temperature high and low status bits. bit 4 of status register 1 indicates that the remote temperature therm limit has been exceeded. this bit gets cleared on a read of status register 1 (see figure 21). bit 5 indicates a remote diode error. this bit is a 1 if a short or open is detected on the remote temperature channel on power-up. if this bit is set to 1 on power-up, it cannot be cleared. bit 6 of status register 2 (003) indicates that the local therm limit has been exceeded. this bit is cleared on a read of status register 2. bit 7 indicates that therm has been pulled low as an input. this bit can also be cleared on a read of status register 2. 5 int rearmed status reg. read temp therm limit therm int 02402-021 figure 21. operation of therm and int signals figure 21 shows the interaction between int and therm . once a critical temperature therm limit is exceeded, both int and therm assert low. reading the status registers clears the interrupt and the int pin goes high. however, the therm pin remains asserted until the measured temperature falls 5c below the exceeded therm limit. this feature can be used to cpu throttle or drive a fan full speed for maximum cooling. note that the int pin for that interrupt source is not rearmed until the temperature has fallen below the therm limit C5c. this prevents unnecessary interrupts from tying up valuable cpu resources. adm1031 rev. 3 | page 17 of 35 | www.onsemi.com fan control modes of operation the adm1031 has four different modes of operation. these modes determine the behavior of the system. 1. automatic fan speed control mode. 2. filtered automatic fan speed control mode. 3. pwm duty cycle select mode (directly sets fan speed under software control). 4. rpm feedback mode. automatic fan speed control the adm1031 has a local temperature channel and two remote temperature channels, which can be connected to an on-chip diode-connected transistor on a cpu. these three temperature channels can be used as the basis for an automatic fan speed control loop to drive fans using pulse width modulation (pwm). how does the control loop work? the automatic fan speed control loop is shown in figure 22. max fan speed min temperature t min t max = t min + t range spin-up for seconds 02402-022 figure 22. automatic fan speed control loop t min is the temperature at which the fan should switch on and run at minimum speed. the fan only turns on once the temperature being measured rises above the tmin value programmed. the fan spins up for a predetermined time (default = 2 seconds). see the fan spin-up section for more details. t range is the temperature range over which the adm1031 automatically adjusts the fan speed. as the temperature increases beyond t min , the pwm_out duty cycle increases accordingly. the t range parameter actually defines the fan speed vs. temperature slope of the control loop. t max is the temperature at which the fan is at its maximum speed. at this temperature, the pwm duty cycle driving the fan is 100%. t max is given by t min + t range . since this parameter is the sum of the t min and t range parameters, it does not need to be programmed into a register on-chip. a hysteresis value of 5c is included in the control loop to prevent the fan continuously switching on and off if the temperature is close to t min . the fan continues to run until the temperature drops 5c below t min . figure 23 shows the different control slopes determined by the t range value chosen, and programmed into the adm1031. t min is set to 0c to start all slopes from the same point. the figure shows how changing the t range value affects the pwm duty cycle vs. temperature slope. temperature ( c) pwm duty cycle (%) 0 100 93 87 80 73 66 60 53 47 40 33 t min 510 20 40 60 80 t max = t min + t range t r a n g e = 8 0 c t r a n g e = 4 0 c t r a n g e = 2 0 c t r a n g e = 1 0 c t r a n g e = 5 c 02402-023 figure 23. pwm duty cycle vs. temperature slope (t range ) figure 24 shows how, for a given t range , changing the t min value affects the loop. increasing the t min value increases the t max (temperature at which the fan runs full speed) value, since t max = t min + t range . note, however, that the pwm duty cycle vs. temperature slope remains exactly the same. changing the t min value merely shifts the control slope. the t min can be changed in increments of 4c. temperature ( c) pwm duty cycle (%) 0 100 93 87 80 73 66 60 53 47 40 33 t min 20 40 60 80 t max = t min + t range t r a n g e = 4 0 c t r a n g e = 4 0 c t r a n g e = 4 0 c 02402-024 figure 24. effect of increasing t min value on control loop adm1031 rev. 3 | page 18 of 35 | www.onsemi.com fan spin-up as mentioned in the how does the control loop work? section, once the temperature being measured exceeds the t min value programmed, the fan turns on at minimum speed (default = 33% duty cycle). however, the problem with fans being driven by pwm is that 33% duty cycle is not enough to reliably start the fan spinning. the solution is to spin the fan up for a predetermined time, and once the fan has spun up, its running speed can be reduced in line with the temperature being measured. the adm1031 allows fan spin-up times between 200 ms and 8 seconds. bits <2:0> of fan characteristics register 1 (register 020) and fan characteristic register 2 (register 021) program the fan spin-up times. table 9. fan spin-up times bits 2:0 spin-up time (fan characteristics registers 1, 2) 000 200 ms 001 400 ms 010 600 ms 011 800 ms 100 1 sec 101 2 sec (default) 110 4 sec 111 8 sec once the automatic fan speed control loop parameters have been chosen, the adm1031 device can be programmed. the adm1031 is placed into automatic fan speed control mode by setting bit 7 of configuration register 1 (register 000). the device powers up in automatic fan speed control mode by default. the control mode offers further flexibility in that the user can decide which temperature channel/channels control each fan. table 10. auto mode fan behavior bits 6, 5 control operation (configuration register 1) 00 remote temperature 1 controls fan 1 remote temperature 2 controls fan 2 01 remote temperature 1 controls fan 1 and 2 10 remote temperature 2 controls fan 1 and 2 11 maximum speed calculated by local and remote temperature channels controls fans 1 and 2 when bit 5 and bit 6 of configuration register 1 are both set to 1, increased flexibility is offered. the local and remote temperature channels can have independently programmed control loops with different control parameters. whichever control loop calculates the fastest fan speed based on the temperature being measured, drives the fans. figure 25 and figure 26 show how the fans pwm duty cycle is determined by two independent control loops. this is the type of auto mode fan behavior seen when bit 5 and bit 6 of configuration register 1 are set to 11. figure 25 shows the control loop for the local temperature channel. its t min value has been programmed to 20c, and its t range value is 40c. the local temperatures t max is thus 60c. figure 26 shows the control loop for the remote temperature channel. its t min value has been set to 0c, while its t range = 80c. therefore, the remote temperatures t max value is 80c. consider if both temperature channels measure 40c. both control loops calculate a pwm duty cycle of 66%. therefore, the fan is driven at 66% duty cycle. if both temperature channels measure 20c, the local channel calculates 33% pwm duty cycle, while the remote 1 channel calculates 50% pwm duty cycle. thus, the fans are driven at 50% pwm duty cycle. consider the local temperature measuring 60c while the remote 1 tempera- ture is measuring 70c. the pwm duty cycle calculated by the local temperature control loop is 100% (because the temperature = t max ). the pwm duty cycle calculated by the remote 1 temperature control loop at 70c is approximately 90%. therefore, the fan runs full-speed (100% duty cycle). remember, that the fan speed is based on the fastest speed calculated, and is not necessarily based on the highest temperature measured. depending on the control loop parameters programmed, a lower temperature on one channel, can actually calculate a faster speed than a higher temperature on the other channel. local temperature ( c) pwm duty cycle (%) 0 100 93 87 80 73 66 60 53 47 40 33 t min 20 40 60 t max = t min + t range t r a n g e = 4 0 c 02402-025 figure 25. maximum speed calculated by local temperature control loop drives fan adm1031 rev. 3 | page 19 of 35 | www.onsemi.com remote temperature ( c) pwm duty cycle (%) 0 100 93 87 80 73 66 60 53 47 40 33 t min 20 40 70 80 t max = t min + t range t r a n g e = 8 0 c 02402-026 figure 26. maximum speed calculated by remote temperature control loop drives fan programming the automatic fan speed control loop 1. program a value for t min . 2. program a value for the slope t range . 3. t max = t min + t range . 4. program a value for fan spin-up time. 5. program the desired automatic fan speed control mode behavior, that is, which temperature channel controls the fan. 6. select automatic fan speed control mode by setting bit 7 of configuration register 1. other control loop parameters it should be noted that changing the minimum pwm duty cycle affects the control loop behavior. slope 1 of figure 27 shows t min set to 0c and the t range chosen is 40c. in this case, the fans pwm duty cycle varies over the range 33% to 100%. the fan runs full-speed at 40c. if the minimum pwm duty cycle at which the fan runs at t min is changed, its effect can be seen on slope 2 and slope 3. take case 2, where the minimum pwm duty cycle is reprogrammed from 33% (default) to 53%. temperature ( c) 0 100 93 87 80 66 60 47 40 33 t min 16 28 40 60 pwm duty cycle (%) 73 53 3 1 2 t r a n g e = 4 0 c 02402-027 figure 27. effect of changing minimum duty cycle on control loop with fixed t min and t range values the fan actually reaches full speed at a much lower temperature, 28c. case 3 shows that when the minimum pwm duty cycle is increased to 73%, the temperature at which the fan runs full speed is 16c. therefore, the effect of increasing the minimum pwm duty cycle, with a fixed t min and fixed t range , is that the fan actually reaches full speed (t max ) at a lower temperature than t min + t range . how can t max be calculated? in automatic fan speed control mode, the register that holds the minimum pwm duty cycle at t min , is the fan speed configuration register (register 022). table 11 shows the relationship between the decimal values written to the fan speed configuration register and pwm duty cycle obtained. table 11. programming pwm duty cycle decimal value pwm duty cycle 00 0% 01 7% 02 14% 03 20% 04 27% 05 33% (default) 06 40% 07 47% 08 53% 09 60% 10 (00a) 67% 11 (00b) 73% 12 (00c) 80% 13 (00d) 87% 14 (00e) 93% 15 (00f) 100% the temperature at which the fan runs full-speed (100% duty cycle) is given by: t max = t min + (( max dc C min dc ) t range /10) where: t max = temperature at which fan runs full-speed. t min = temperature at which fan turns on. max dc = maximum duty cycle (100%) = 15 decimal. min dc = duty cycle at t min , programmed in to fan speed configuration register (default = 33% = 5 decimal). t range = pwm duty cycle vs. temperature slope. example 1 t min = 0 c, t range = 40 c min dc = 53% = 8 decimal (table 11) calculate t max . t max = t min + (( max dc ? min dc ) t range /10) t max = 0 + ((100% dc ? 53% dc) 40/10) t max = 0 + ((15 ? 8) 4) = 28 t max = 28c (as seen on slope 2 of figure 27) adm1031 rev. 3 | page 20 of 35 | www.onsemi.com example 2 t min = 0c, t range = 40c min dc = 73% = 11 decimal (table 11) calculate t max . t max = t min + (( max dc C min dc) t range /10) t max = 0 + ((100% dc C 73% dc) 4 0/10) t max = 0 + ((15 C 11) 4) = 16 t max = 16c (as seen on slope 3 of figure 27) example 3 t min = 0c, t range = 40c min dc = 33% = 5 decimal (table 11) calculate t max . t max = t min + (( max dc C min dc ) t range /10) t max = 0 + ((100% dc C 33% dc) 40/10) t max = 0 + ((15 C 5) 4 ) = 40 t max = 40c (as seen on slope 1 of figure 27) in this case, since the minimum duty cycle is the default 33%, the equation for t max reduces to t max = t min + (( max dc C min dc ) t range /10) t max = t min + ((15 C 5) t range /10) t max = t min + (10 t range /10) t max = t min + t range relevant registers for automatic fan speed control mode register 000 configuration register 1 <7> logic 1 selects automatic fan speed control, logic 0 selects software control (default = 1). <6:5> 00 = remote temp 1 controls fan 1, remote temp 2 controls fan 2. 01 = remote temp 1 controls fan 1 and fan 2 10 = remote temp 2 controls fan 1 and fan 2 11 = fastest calculated speed controls fan 1 and 2 register 020, 021 fan characteristics registers 1, 2 <2:0> fan x spin-up time. 000 = 200 ms 001 = 400 ms 010 = 600 ms 011 = 800 ms 100 = 1 sec 101 = 2 sec (default) 110 = 4 sec 111 = 8 sec <5:3> pwm frequency driving the fan. 000 = 11.7 hz 001 = 15.6 hz 010 = 23.4 hz 011 = 31.25 hz (default) 100 = 37.5 hz 101 = 46.9 hz 110 = 62.5 hz 111 = 93.5 hz <7:6> speed range n; defines the lowest fan speed that can be measured by the device. 00 = 1: lowest speed = 2647 rpm 01 = 2: lowest speed = 1324 rpm 10 = 4: lowest speed = 662 rpm 11 = 8: lowest speed = 331 rpm register 0 22 fan speed configuration register <3:0> min speed: this nibble contains the speed at which the fan runs when the temperature is at t min . the default is 005, meaning that the fan runs at 33% duty cycle when the temperature is at t min . <7:4> min speed: determines the minimum pwm cycle for fan 2 in automatic fan speed control mode. register 024 local temperature t min /t range <7:3> local temperature t min . these bits set the temperature at which the fan turns on when under auto fan speed control. t min can be programmed in 4c increments. 00000 = 0c 00001 = 4c 00010 = 8c 00011 = 12c | | 01000 = 32c (default) | | 11110 = 120c 11111 = 124c <2:0> local temperature t range . this nibble sets the tem- perature range over which automatic fan speed control takes place. 000 = 5c 001 = 10c 010 = 20c 011 = 40c 100 = 80c adm1031 rev. 3 | page 21 of 35 | www.onsemi.com register 025, 026 remote 1, 2 temperature t min /t range <7:3> remote temperature t min . sets the temperature at which the fan switches on based on remote x temperature readings. 00000 = 0c 00001 = 4c 00010 = 8c 00011 = 12c | | 01100 = 48c | | 11110 = 120c 11111 = 124c <2:0> remote temperature t range . this nibble sets the temperature range over which the fan is controlled based on remote temperature readings. 000 = 5c 001 = 10c 010 = 20c 011 = 40c 100 = 80c filtered control mode the automatic fan speed control loop reacts instantaneously to changes in temperature, that is, the pwm duty cycle responds immediately to temperature change. in certain circumstances, we do not want the pwm output to react instantaneously to temperature changes. if significant variations in temperature are found in a system, the fan speed changes, which could be obvious to someone in close proximity. one way to improve the systems acoustics would be to slow down the loop so that the fan ramps slowly to its newly calculated fan speed. this also ensures that temperature transients are effectively ignored, and the fans operation is smooth. there are two means by which to apply filtering to the automatic fan speed control loop. the first method is to ramp the fan speed at a predetermined rate, to its newly calculated value instead of jumping directly to the new fan speed. the second approach involves changing the on-chip adc sample rate, to change the number of temperature readings taken per second. the filtered mode on the adm1031 is invoked by setting bit 0 of the fan filter register (register 023) for fan 1 and bit 1 for fan 2. once the fan filter register has been written to, and all other control loop parameters (such as t min , t range ) have been programmed, the device can be placed into automatic fan speed control mode by setting bit 7 of configuration register 1 (register 000) to 1. effect of ramp rate on filtered mode bits <6:5> of the fan filter register determine the ramp rate in filtered mode. the pwm_out signal driving the fan has a period, t, given by the pwm_out drive frequency, f, since t = 1/f. for a given pwm period, t, the pwm period is subdivided in to 240 equal time slots. one time slot corresponds to the smallest possible increment in pwm duty cycle. a pwm signal of 33% duty cycle is thus high for 1/3 240 time slots and low for 2/3 240 time slots. therefore, 33% pwm duty cycle corresponds to a signal that is high for 80 time slots and low for 160 time slots. pwm_out 33% duty cycle 80 time slots 160 time slots pwm output (one period = 240 time slots 02402-028 figure 28. 33% pwm duty cycle represented in time slots the ramp rates in filtered mode are selectable between 1, 2, 4, and 8. the ramp rates are actually discrete time slots. for example, if the ramp rate = 8, then eight time slots are added to the pwm_out high duty cycle each time the pwm_out duty cycle needs to be increased. figure 29 shows how the filtered mode algorithm operates. read temperature calculate new pwm duty cycle increment previous pwm value by ramp rate decrement previous pwm value by ramp rate is new pwm value > previous value? yes no 02402-029 figure 29. filtered mode algorithm the filtered mode algorithm calculates a new pwm duty cycle based on the temperature measured. if the new pwm duty cycle value is greater than the previous pwm value, the previous pwm duty cycle value is incremented by either 1, 2, 4, or 8 time slots (depending on the setting of bits <6:5> of the fan filter register). if the new pwm duty cycle value is less than the previous pwm value, the previous pwm duty cycle is decremented by 1, 2, 4, or 8 time slots. each time the pwm duty cycle is incremented or decremented, it is stored as the previous pwm duty cycle for the next comparison. adm1031 rev. 3 | page 22 of 35 | www.onsemi.com what does an increase of 1, 2, 4, or 8 time slots actually mean in terms of pwm duty cycle? a ramp rate of 1 corresponds to one time slot, which is 1/240 of the pwm period. in filtered auto fan speed control mode, incrementing or decrementing by 1 changes the pwm output duty cycle by 0.416%. table 12. effect of ramp rates on pwm_out ramp rate pwm duty cycle change 1 0.416% 2 0.833% 4 1.66% 8 3.33% so programming a ramp rate of 1, 2, 4, or 8 simply increases or decreases the pwm duty cycle by the amounts shown in table 12, depending on whether the temperature is increasing or decreasing. figure 30 shows remote temperature plotted against pwm duty cycle for filtered mode. the adc sample rate is the highest sample rate; 11.25 khz. the ramp rate is set to 8, which would correspond to the fastest ramp rate. with these settings, it took approximately 12 seconds to go from 0% duty cycle to 100% duty cycle (full- speed). the t min value = 32c and the t range = 80c. even though the temperature increased very rapidly, the fan gradually ramps up to full speed. 140 pwm duty cycle 0 012 time (s) r temp ( c) 120 100 80 60 40 20 120 0 pwm duty cycle (%) 100 80 60 40 20 r temp 02402-030 figure 30. filtered mode with ramp rate = 8 figure 31 shows how changing the ramp rate from 8 to 4 affects the control loop. the overall response of the fan is slower. because the ramp rate is reduced, it takes longer for the fan to achieve full running speed. in this case, it took approximately 22 seconds for the fan to reach full speed. 120 pwm duty cycle 0 022 time (s) r temp ( c) 110 80 60 40 20 120 140 0 pwm duty cycle (%) 100 80 60 40 20 r temp 02402-031 figure 31. filtered mode with ramp rate = 4 figure 32 shows the pwm output response for a ramp rate of 2. in this instance the fan took about 54 seconds to reach full running speed. 140 pwm duty cycle 0 054 time (s) r temp ( c) 120 100 80 60 40 20 120 0 pwm duty cycle (%) 100 80 60 40 20 r temp 02402-032 figure 32. filtered mode with ramp rate = 2 finally, figure 33 shows how the control loop reacts to temperature with the slowest ramp rate. the ramp rate is set to 1, while all other control parameters remain the same. with the slowest ramp rate selected, it took 112 seconds for the fan to reach full speed. 120 pwm duty cycle 0 0 112 time (s) pwm duty cycle (%) 110 80 60 40 20 140 0 r temp ( c) 120 100 80 60 40 20 r temp 02402-033 figure 33. filtered mode with ramp rate = 1 adm1031 rev. 3 | page 23 of 35 | www.onsemi.com as can be seen from figure 30 through figure 33, the rate at which the fan reacts to temperature change is dependent on the ramp rate selected in the fan filter register. the higher the ramp rate, the faster the fan reaches the newly calculated fan speed. figure 34 shows the behavior of the pwm output as temperature varies. as the temperature rises, the fan speed ramps up. small drops in temperature do not affect the ramp-up function because the newly calculated fan speed is still higher than the previous pwm value. the filtered mode allows the pwm output to be made less sensitive to temperature variations. this is dependent on the ramp rate selected and the adc sample rate programmed into the fan filter register. 90 pwm duty cycle 0 time (s) pwm duty cycle (%) 80 70 60 30 40 50 10 20 90 0 r temp ( c) 80 70 60 40 50 30 10 20 r temp 02402-034 figure 34. how fan reacts to temperature variation in filtered mode effect of adc sample ra te on filtered mode the second way to change the filtered mode characteristics is to adjust the adc sample rate. the faster the adc sample rate, the more temperature samples are obtained per second. one way to apply filtering to the control loop is to slow down the adc sampling rate. this means that the number of iterations of the filtered mode algorithm per second is effectively reduced. if the number of temperature measurements per second is reduced, how often the pwm_out signal controlling the fan is updated is also reduced. bits <4:2> of the fan filter register (register 023) set the adc sample rate. the default adc sample rate is 1.4 khz. the adc sample rate is selectable from 87.5 hz to 11.2 khz. table 13 shows how many temperature samples are obtained per second, for each of the adc sample rates. table 13. temperature updates per second adc sample rate temperature updates/sec 87.5 hz 0.0625 175 hz 0.125 350 hz 0.25 700 khz 0.5 1.4 khz 1 (default) 2.8 khz 2 5.6 khz 4 11.2 khz 8 relevant registers for filtered automatic fan speed control mode in addition to the registers used to program the normal automatic fan speed control mode, the following register needs to be programmed. register 023 fan filter register <7> spin-up disable: when this bit is set to 1, fan spin-up is disabled. (default = 0) <6:5> ramp rate: these bits set the ramp rate for filtered mode. 00 = 1 (0.416% duty cycle change) 01 = 2 (0.833% duty cycle change) 10 = 4 (1.66% duty cycle change) 11 = 8 (3.33% duty cycle change) <4:2> adc sample rate. 000 = 87.5 hz 001 = 175 hz 010 = 350 hz 011 = 700 hz 100 = 1.4 khz (default) 101 = 2.8 khz 110 = 5.6 khz 111 = 11.2 khz <1> fan 2 filter enable: when this bit is set to 1, it enables filtering on fan 2. default = 0. <0> fan 1 filter enable: when this bit is set to 1, it enables filtering on fan 1. default = 0. programming the filtered automatic fan speed control loop 1. program a value for t min . 2. program a value for the slope t range . 3. t max = t min + t range . 4. program a value for fan spin-up time. 5. program the desired automatic fan speed control mode behavior, that is, which temperature channel controls the fan. 6. program a ramp rate for the filtered mode. 7. program the adc sample rate in the fan filter register. 8. set bit 0 to enable fan filtered mode for fan 1. 9. set bit 1 to enable the fan filtered mode for fan 2. 10. select automatic fan speed control mode by setting bit 7 of configuration register 1. adm1031 rev. 3 | page 24 of 35 | www.onsemi.com pwm duty cycle select mode the adm1031 can operate under software control by clearing bit 7 of configuration register 1 (register 000). this allows the user to directly control pwm duty cycle for each fan. clearing bit 5 and bit 6 of configuration register 1 allows fan control by varying pwm duty cycle. values of duty cycle between 0% and 100% can be written to the fan speed configuration register (022) to control the speed of each fan. table 14 shows the relationship between hex values written to the fan speed configuration register and pwm duty cycle obtained. table 14. pwm duty cycle select mode hex value pwm duty cycle 00 0% 01 7% 02 14% 03 20% 04 27% 05 33% 06 40% 07 47% 08 53% 09 60% 0a 67% 0b 73% 0c 80% 0d 87% 0e 93% 0f 100% bits <3:0> set the pwm duty cycle for fan 1; bits <7:4> set the pwm duty cycle for fan 2. rpm feedback mode the second method of fan speed control under software is rpm feedback mode. this involves programming the desired fan rpm value to the device to set fan speed. the advantages include a very tightly maintained fan rpm over the fans life, and virtually no acoustic pollution due to fan speed variation. fans typically have manufacturing tolerances of 20%, meaning a wide variation in speed for a typical batch of identical fan models. if it is required that all fans run at exactly 5000 rpm, it can be necessary to specify fans with a nominal fan speed of 6250 rpm. however, many of these fans run too fast and make excess noise. a fan with nominal speed of 6250 rpm could run as fast as 7000 rpm at 100% pwm duty cycle. rpm mode allows all of these fans to be programmed to run at the desired rpm value. clearing bit 7 of configuration register 1 (register 000) to 0 places the adm1031 under software control. once under soft- ware control, the device can be placed into rpm feedback mode by writing to bit 5 and bit 6 of configuration register 1. writing a 1 to bit 5 and bit 6 selects rpm feedback mode for each fan. once rpm feedback mode has been selected, the required fan rpm can be written to the fan tach high limit registers (010, 011). the rpm feedback mode function allows a fan rpm value to be programmed into the device, and the adm1031 maintains the selected rpm value by monitoring the fan tach and speeding up the fan as necessary, should the fan start to slow down. conversely, should the fan start to speed up due to aging, the rpm feedback slows the fan down to maintain the correct rpm speed. the value to be programmed into each fan tach high limit register is given by: count = ( f 60)/ r n where: f = 11.25 khz r = desired rpm value n = speed range; must be set to 2 the speed range, n , really determines what the slowest fan speed measured can be before generating an interrupt. the slowest fan speed is measured when the count value reaches 255. since n = 2 count = ( f 60)/r n r = ( f 60)/count n r = (11250 60)/255 2 r = (675000)/510 r = 1324 rpm, fan fail detect speed programming rpm values in rpm feedback mode rather than writing a value such as 5000 to a 16-bit register, an 8-bit count value is programmed instead. the count to be programmed is given by count = ( f 60)/ r n where: f = 11.25 khz r = desired rpm value n = speed range = 2 example 1: if the desired value for rpm feedback mode is 5000 rpm, the count to be programmed is count = ( f 60)/ r n since the desired rpm value, r , is 5000 rpm, the value for count is: n = 2: count = (11250 60)/5000 2 count = 675000/10000 count = 67 (assumes 2 tach pulses/rev) adm1031 rev. 3 | page 25 of 35 | www.onsemi.com example 2: if the desired value for rpm feedback mode is 3650 rpm, the count to be programmed is count = ( f 60)/ r n since the desired rpm value, r, is 3650 rpm, the value for count is: n = 2: count = (11250 60)/3650 2 count = 675000/7300 count = 92 (assumes 2 tach pulses/rev) once the count value has been calculated, it should be written to the fan tach high limit register. it should be noted that in rpm feedback mode, there is no high limit register for underspeed detection that can be programmed as there are in the other fan speed control modes. the only time each fan indicates a fan failure condition is whenever the count reaches 255. since the speed range n = 2, the fan fails if its speed drops below 1324 rpm. programming rpm values 1. choose the rpm value to be programmed. 2. set speed range value n = 2. 3. calculate count value based on rpm and speed range values chosen. use the count equation to calculate the count value. 4. clear bit 7 of configuration register 1 (register 000) to place the adm1031 under software control. 5. write a 1 to bit 5 of configuration register 1 to place the device in rpm feedback mode. 6. write the calculated count value to the fan tach high limit register (register 010). the fan speed now goes to the desired rpm value and maintains that fan speed. rpm feedback mode limitations rpm feedback mode only controls fan rpm over a limited fan speed range of about 75% to 100%. however, this should be enough range to overcome fan-manufacturing tolerance. in practice, however, the program must not function at too low an rpm value for the fan to run at, or the rpm mode does not operate. to find the lowest rpm value allowed for a given fan, do the following: 1. run the fan at 53% pwm duty cycle in software mode. clear bit 5 and bit 7 of configuration register 1 (register 000) to enter pwm duty cycle mode. write 008 to the fan speed configuration register (register 022) to set the pwm output to 53% duty cycle. 2. measure the fan rpm. this represents the fan rpm below which the rpm mode fails to operate. do not program a lower rpm than this value when using rpm feedback mode. 3. ensure that speed range n = 2 when using rpm feedback mode. adm1031 rev. 3 | page 26 of 35 | www.onsemi.com fan drive and speed measurement fans come in a variety of different options. one distinguishing feature of fans is the number of poles that a fan has internally. the most common fans available have four, six, or eight poles. the number of poles the fan has generally affects the number of pulses per revolution the fan outputs. if the adm1031 is used to drive fans other than 4-pole fans that output 2 tach pulses/revolution, then the fan speed measurement equation needs to be adjusted to calculate and display the correct fan speed, and also to program the correct count value in rpm feedback mode. fan speed measurement equations for a 4-pole fan (2 tach pulses/rev): fan rpm = ( f 60)/ cou nt n for a 6-pole fan (3 tach pulses/rev): fan rpm = ( f 60)/( count n 1.5) for an 8-pole fan (4 tach pulses/rev): fan rpm = ( f 60)/( count n 2) if in doubt as to the number of poles the fans used have, or the number of tach output pulses/rev, consult the fan manufacturers data sheet, or contact the fan vendor for more information. fan drive using pwm control the external circuitry required to drive a fan using pwm control is extremely simple. a single nmos fet is the only drive transistor required. the specifications of the mosfet depend on the maximum current required by the fan being driven. typical notebook fans draw a nominal 170 ma, and so sot devices can be used where board space is a constraint. if driving several fans in parallel from a single pwm output, or driving larger server fans, the mosfet needs to handle the higher current requirements. the only other stipulation is that the mosfet should have a gate voltage drive, v gs < 3.3 v, for direct interfacing to the pwm_out pin. the mosfet should also have a low on-resistance to ensure that there is not significant voltage drop across the fet. this would reduce the maximum operating speed of the fan. figure 35 shows how a 3-wire fan can be driven using pwm control. +v 5v or 12v fan q1 ndt3055l adm1031 pwm_out tach/ain tach 10k typical 10k typical 3.3v 3.3v 02402-035 figure 35. interfacing the adm1031 to a 3-wire fan the ndt3055l n-type mosfet was chosen since it has 3.3 v gate drive, low on-resistance, and can handle 3.5 a of current. other mosfets can be substituted based on the systems fan drive requirements. figure 36 shows how a 2-wire fan can be connected to the adm1031. this circuit allows the speed of the 2-wire fan to be measured even though the fan has no dedicated tach signal. a series r sense resistor in the fan circuit converts the fan commutation pulses into a voltage. this is ac-coupled into the adm1031 through the 0.01 f capacitor. on-chip signal conditioning allows accurate monitoring of fan speed. for typical notebook fans drawing approximately 170 ma, a 2 r sense value is suitable. for fans such as desktop or server fans that draw more current, r sense can be reduced. the smaller r sense is, the better, since more voltage is developed across the fan, and the fan then spins faster. +v 5v or 12v fan adm1031 tach/ain pwm_out tach 10k typical 0.01 f 3.3v q1 ndt3055l r sense (2w typical) 02402-036 figure 36. interfacing the adm1031 to a 2-wire fan figure 37 shows a typical plot of the sensing waveform at the tach/ain pin. the most important thing is that the negative- going spikes are more than 250 mv in amplitude. this is the case for most fans when r sense = 2 . the value of r sense can be reduced as long as the voltage spikes at the tach/ain pin are greater than 250 mv. this allows fan speed to be reliably determined. adm1031 rev. 3 | page 27 of 35 | www.onsemi.com 02402-037 figure 37. fan speed sensing waveform at tach/ain pin fan speed measurement the fan counter does not count the fan tach output pulses directly, because the fan speed can be less than 1000 rpm and it would take several seconds to accumulate a reasonably large and accurate count. instead, the period of the fan revolution is measured by gating an on-chip 11.25 khz oscillator into the input of an 8-bit counter. the fan speed measuring circuit is initialized on the rising edge of a pwm high output if fan speed measurement is enabled (bit 2 and bit 3 of configuration register 2 = 1). it then starts counting on the rising edge of the second tach pulse and counts for two fan tach periods, until the rising edge of the fourth tach pulse, or until the counter overranges if the fan tach period is too long. the measurement cycle repeats until monitoring is disabled. the fan speed measurement is stored in the fan speed reading register at address 008, 009. the fan speed count is given by: count = ( f 60)/ r n where: f = 11.25 khz r = fan speed in rpm. n = speed range (either 1, 2, 4, or 8) the frequency of the oscillator can be adjusted to suit the expected running speed of the fan by varying n , the speed range. the oscillator frequency is set by bit 7 and bit 6 of fan characteristics register 1 (020) and fan characteristics register 2 (021) as shown in table 15. figure 38 shows how the fan measurements relate to the pwm_out pulse trains. table 15. oscillator frequencies bit 7 bit 6 n oscillator frequency (khz) 0 0 1 11.25 0 1 2 5.625 1 0 4 2.812 1 1 8 1.406 clock config 2 reg. bit 2 fan input start of monitoring cycle fan measurement period 02402-038 figure 38. fan speed measurement in situations where different output drive circuits are used for fan drive, it can be desirable to invert the pwm drive signal. setting bit 3 of configuration register 1 (000) to 1, inverts the pwm_out signal. this makes the pwm_out pin high for 100% duty cycle. bit 3 of configuration register 1 should gener- ally be set to 1 when using an n-mos device to drive the fan. if using a p-mos device, bit 3 of configuration register 1 should be cleared to 0. fan faults the fan_fault output (pin 8) is an active-low, open-drain output used to signal fan failure to the system processor. writing a logic 1 to bit 4 of configuration register 1 (000) enables the fan_fault output pin. the fan_fault output is enabled by default. the fan_fault output asserts low only when five consecutive interrupts are generated by the adm1031 device due to the fan running underspeed, or if the fan is completely stalled. note that the fan tach high limit must be exceeded by at least one before a fan_fault can be generated. for example, if we are only interested in getting a fan_fault if the fan stalls, then the fan speed value is 0ff for a failed fan. therefore, we should make the fan tach high limit = 0fe to allow fan_fault to be asserted after five consecutive fan tach failures. figure 39 shows the relationship between int , fan_fault , and the pwm drive channel. the pwm_out channel is driving a fan at some pwm duty cycle, 50% for example, and the fans tach signal (or fan current for a 2-wire fan) is being monitored at the tach/ain pin. tach pulses are being generated by the fan, during the high time of the pwm duty cycle train. the tach is pulled high during the off time of the pwm train because the fan is connected high-side to the n- mos device. suppose the fan has twice previously failed its fan speed measurement. looking at figure 39, pwm_out is brought high for two seconds, to restart the fan if it has stalled. sometime later a third tach failure occurs. this is evident by the tach signal being low during the high time of the pwm pulse, causing the fan speed reading register to reach its maximum count of 255. since adm1031 rev. 3 | page 28 of 35 | www.onsemi.com the tach limit has been exceeded, an interrupt is generated on the int pin. the fan fault bit (bit 1) of interrupt status register 1 (register 002) is also asserted. once the processor has acknowledged the int by reading the status register, the int is cleared. pwm_out is then brought high for another two seconds to restart the fan. subsequent fan failures cause int to be reasserted and the pwm_out signal is brought high for two seconds (fan spin-up default) each time to restart the fan. once the fifth tach failure occurs, the failure is deemed to be catastrophic and the fan_fault pin is asserted low. pwm_out is brought high to attempt to restart the fan. the int pin continues to generate interrupts after the assertion of fan_fault since tach measurement continues even after fan failure. should the fan recover from its failure condition, the fan_fault signal is negated, and the fan returns to its normal operating speed. figure 40 shows a typical application circuit for the adm1031. temperature monitoring can be based around a cpu diode or discrete transistor measuring thermal hotspots. either 2- or 3- wire fans can be monitored by the adm1031, as shown. pwm_out tach/ain int fan_fault status reg read to clear interrupt full speed 2 secs 2 secs 2 secs 3rd tach failure 4th tach failure 5th tach failure continuing tach failure 02402-039 figure 39. operation of fan_fault and interrupt pins sda scl gnd v cc 1 2 3 4 16 15 14 13 adm1031 5 12 6 7 8 9 10 11 int (smbalert) tach1/ain1 d1+ d1?/nti add therm fan_fault pwm_out2 tach2/ain2 fan_fault to signal fan failure condition cpu interrupt sda scl 2n3904 or pentium iii cpu thermal diode therm signal to throttle cpu clock 3.3v 3.3v 5v tach fan1 1 3-wire fan pwm_out1 d2+ d2? ndt3055l (nmos) 10kv typ 3.3v 10kv typ 3.3v 5v max (do not connect to 12v) 10kv typ 2.2kv 3.3v 2.2kv 3.3v 10kv typ 3.3v 10kv typ 10kv typ 3.3v 5v fan2 2-wire fan ndt3055l (n-mos) r sense 0.01mf 2n3904 or pentium iii cpu thermal diode 1 in actual application, both fans must be 2-wire or 3-wire type. a single bit controls whether tach1/ain1 and tach2/ain2 are analog or digital inputs. 02402-040 figure 40. typical application circuit adm1031 rev. 3 | page 29 of 35 | www.onsemi.com table 16. registers register name address a7-a0 in hex comments value registers 0x08C0x1e see table 17. device id register 0x3d this location contains the device identification number. since this device is the adm1031, this register contains 0x31. this register is read only. company id 0x3e this location contains the company iden tification number (0x41). th is register is read only. therm behavior/revision 0x3f this location contains the revision number of the device. the lower four bits reflect device revisions [3:0]. bit 7 of this register is the therm -to-fan enable bit. see table 21. configuration register 1 0x00 see table 18. (power-on value = 1001 0000) configuration register 2 0x01 see table 19. (power-on value = 0111 1111) status register 1 0x02 see table 20. (power-on value = 0000 0000) status register 2 0x03 see table 21. (power-on value = 0000 0000) manufacturers test register 0x07 this register is used by the manufacturer for test purposes only. this register should not be read from or written to in normal operation. fan characteristics register 1 0x20 see table 23. (power-on value = 0101 1101) fan characteristics register 2 0x21 see table 24 . (power-on value = 0101 1101) fan speed configuration register 0x22 see table 25. (power-on value = 0101 0101) fan filter register 0x23 see table 26. (power-on value = 0101 0000) local temperature t min /t range 0x24 see table 27. (power-on value = 0100 0001) remote 1 temperature t min /t range 0x25 see table 28. (power-on value = 0110 0001) remote 2 temperature t min /t range 0x26 see table 29. (power-on value = 0110 0001) table 17. value registers address read/write description 0x06 read only extended temperature resolution (see table 22). 0x08 read/write fan 1 speed. this register contains the value of the fan 1 tach measurement. 0x09 read/write fan 2 speed. this register contains the value of the fan 2 tach measurement. 0x0a read only local temperature value. this register contains the 8 msbs of the local temperature measurement. 0x0b read only remote 1 temperature value. this register contains the 8 msbs of the remote 1 temperature reading. 0x0c read only remote 2 temperature value. this register contains the 8 msbs of the remote 2 temperature reading. 0x0d read/write local temperature offset. see table 31. (power-on default = 00h) 0x0e read/write remote 1 temperature offset. see table 32. (power-on default = 00h) 0x0f read/write remote 2 temperature offset. see table 33. (power-on default = 00h) 0x10 read/write fan 1 tach high limit. this register contains the limit for the fan 1 tach measurement. because the tach circui t counts between pulses, a slow fan results in a large measure value, so exceeding the limit is the way to detect a slow or stalled fan. (power-on default = ffh) 0x11 read/write fan 2 tach high limit. this register contains the limit for the fan 2 tach measurement. because the tach circui t counts between pulses, a slow fan results in a large measured value, so exceeding the limit is the way to detect a slow or stalled fan. (power-on default = ffh) 0x14 read/write local temperature high limit (power-on default 60c) 0x15 read/write local temperature low limit (power-on default 0c) 0x16 read/write local temperature therm limit (power-on default 70c) 0x18 read/write remote 1 temperature high limit (power-on default 80c) 0x19 read/write remote 1 temperature low limit (power-on default 0c) 0x1a read/write remote 1 temperature therm limit (power-on default 100c) 0x1c read/write remote 2 temperature high limit (power-on default 80c) 0x1d read/write remote 2 temperature low limit (power-on default 0c) 0x1e read/write remote 2 temperature therm limit (power-on default 100c) adm1031 rev. 3 | page 30 of 35 | www.onsemi.com table 18. register 000 configuration register 1 power-on default = 90h bit name r/ w description 0 monitor read/write setting this bit to a 1 enables monitoring of temperature and enables measurement of the fan tach signals. (power-up default=0) 1 int enable read/write setting th is bit to a 1 enables the int output. 1= enabled 0= disabled (power-up default=0) 2 tach/ain read/write clearing this bit to 0 selects digital fan speed measurement via the tach pins. setting this bit to 1 configures the tach pins as analog inputs that can measure the speed of 2-wire fans via a sense resistor. (power-up default=0) 3 pwm invert read/write setting this bit to 1 inverts the pwm signal on the output pins. (power-up default=0) 4 fan fault enable read/write logic 1 enables fan_fault pin; logic 0 disables fan_fault output. (power-up default=1) 6- 5 pwm mode read/write these two bits control the beha vior of the fans in auto fan speed control mode. 00 = remote temp 1 controls fan 1; remote temp 2 controls fan 2. 01 = remote temp 1 controls fan 1 and fan 2. 10 = remote temp 2 controls fan 1 and fan 2. 11 = max of local temp and remote temp 1 and 2 drives fans 1 and 2. these two bits have the following effect in software control mode. 00 = program pwm duty cycles for fans 1 and 2. 11 = program rpm speeds for fans 1 and 2. 7 auto/sw ctrl read/write logic 1 selects automatic fan speed control; logic 0 selects sw control. (power-up default = 1) when under software control, pwm duty cycle or rpm values can be programmed for each fan. table 19. register 001 configuration 2 power-on default = 7fh bit name r/ w description 0 pwm 1 en read/write enables fan 1 pw m output when this bit is a 1. 1 pwm 2 en read/write enables fan 2 pw m output when this bit is a 1. 2 tach 1 en read/write enables tach 1 input when set to 1. 3 tach 2 en read/write enables tach 2 input when set to 1. 4 loc temp en read/write enables interrupts on local temperature channel when set to 1. 5 remote 1 temp en read/write interrupts on remote 1 channel when set to 1. default is normally enabled, except when a diode fault is detected on power-up. 6 remote 2 temp en read/write enables interrupts on remote 2 channel when set to 1. default is normally enabled, except when a diode fault is detected on power-up. 7 sw reset read/write when set to 1, resets the device. self-clears. power-up default = 0. table 20. register 002 status register 1 power-on default = 00h bit name r/ w description 0 alarm 1 speed read only this bit is set to 1 when fan is running at alarm speed. once read, this bit is not reasserted on n ext monitoring cycle, even if the fan is still running at alarm speed. 1 fan 1 fault read only this bit is set to 1 if fan 1 becomes stuck or is running under speed. 2 remote 1 high read only 1 indicates remote 1 high temperature limit has been exceeded. if the temperature is still outside the remote 1 temp high limit, this bit reasserts on next monitoring cycle. 3 remote 1 low read only 1 indicates remote 1 low temperature limit exceeded (below). if the temperature is still outside the remote 1 temp low limit, this bit reasserts on next monitoring cycle. 4 remote 1 therm read only 1 indicates remote 1 temperature therm limit has been exceeded. this bit is cleared on a read of status register 1. 5 remote diode 1 error read only this bit is set to 1 if a short or open is dete cted on the remote 1 temperature channel. this test is only done on power-up, and if set to 1 cannot be cleared by reading the status register 1. 6 local temp high read only this bit is set to 1 if a short or open is dete cted on the remote 1 temperature channel. this test is only done on power-up, and if set to 1 cannot be cleared by reading the status register 1. 7 local temp low read only 1 indicates local temp low limit has been exceeded (below). if the temperature is still outside the local temp low limit, this bit reasserts on next monitoring cycle. adm1031 rev. 3 | page 31 of 35 | www.onsemi.com table 21. register 003 status register 2 power-up default = 00h bit name r/ w description 0 alarm 2 speed read only this bit is set to 1 when fan 2 is running at alarm speed. once read, this bit is not reasserted on next monitoring cycle, even if the fan is still running at alarm speed. 1 fan 2 fault read only this bit is set to 1 if fan 2 becomes stuck or is running under speed. 2 remote 2 high read only 1 indicates remote 2 high temperature limit has been exceeded. if the temperature is still outside the remote 2 temp high limit, this bit reasserts on the next monitoring cycle. 3 remote 2 low read only 1 indicates remote 2 low temperature limit exceeded (below). if the temperature is still outside the remote 2 temp low limit, this bit reasserts on the next monitoring cycle. 4 remote 2 therm read only 1 indicates remote 2 temperature therm limit has been exceeded. this bit is cleared on reading status register 2. 5 remote diode 2 error read only this bit is set to 1 if a short or open is dete cted on the remote 2 temperature channel. this test is only done on power-up, and if set to 1 cannot be cleared by reading status register 2. 6 local therm read only 1 indicates local temperature therm limit has been exceeded. this bit clears on a read of status register 2. 7 therm read only set to 1 when therm is pulled low as an input. this bit clears on a read of status register 2. table 22. register 006 extended temperature resolution power-on default = 00h bit name r/ w description <2:0> remote temp 1 read only holds extended temperature resolution bits for remote 1 channel. <5:3> remote temp 2 read only holds extended temperature resolution bits for remote 2 channel. <7:6> local temp read only holds extended temperature resolution bits for local temperature channel. table 23. register 020 fan characteristics register 1 power-on default = 5dh bit name r/ w description <2:0> fan 1 spin-up read/write these bits contain the fan sp in-up time to allow fan 1 to overcome its own inertia. 000 = 200 ms 001 = 400 ms 010 = 600 ms 011 = 800 ms 100 = 1 sec 101 = 2 sec (default) 110 = 4 sec 111 = 8 sec <5:3> pwm 1 frequency read/write these bits allow programmability of the nominal pwm 1 output frequency driving fan 1. (default = 31 hz.) 000 = 11.7 hz 001 = 15.6 hz 010 = 23.4 hz 011 = 31.25 hz (default) 100 = 37.5 hz 101 = 46.9 hz 110 = 62.5 hz 111 = 93.5 hz <7:6> speed range, n read/write speed range 00 = 1 01 = 2 10 = 4 11 = 8 adm1031 rev. 3 | page 32 of 35 | www.onsemi.com table 24. register 021 fan characteristics register 2 power-on default = 5h bit name r/ w description <2:0> fan 2 spin-up read/write these bits contain the fan sp in-up time to allow fan 2 to overcome its own inertia. 000 = 200 ms 001 = 400 ms 010 = 600 ms 011 = 800 ms 100 = 1 sec 101 = 2 sec (default) 110 = 4 sec 111 = 8 sec <5:3> pwm 2 frequency read/write these bits allow programmability of the nominal pwm 2 output frequency driving fan 1. (default = 31 hz.) 000 = 11.7 hz 001 = 15.6 hz 010 = 23.4 hz 011 = 31.25 hz (default) 100 = 37.5 hz 101 = 46.9 hz 110 = 62.5 hz 111 = 93.5 hz <7:6> speed range, n read/write speed range 00 = 1 01 = 2 10 = 4 11 = 8 table 25. register 022 fan speed configuration register power-on default = 55h bit name r/ w description <3:0> normal/min spd 1 read/write this nibble contains the normal speed value for fan 1. when in automatic fan speed control mode, this nibble contains the minimum speed at which fan 1 runs. default is 0x05 for 33% pwm duty cycle. <7:4> normal/min spd 2 read/write this nibble contains the normal speed value for fan 2. when in automatic fan speed control mode, this nibble contains the minimum speed at which fan 2 runs. default is 0x05 for 33% pwm duty cycle. table 26. register 023 fan filter register power-on default = 50h bit name r/ w description <7> spin-up disable read/write when set to 1, disables fan spin-up. <6:5> ramp rate read/write these bits set the ramp rate. (default = 31 hz) 00 = 1 01 = 2 10 = 4 (default) 11 = 8 <4:2> adc sample rate read/write these bi ts set the sampling rate for the adc. 000 = 87.5 hz 001 = 175 hz 010 = 350 hz 011 = 700 hz 100 = 1.4 khz (default) 101 = 2.8 khz 110 = 5.6 khz 111 = 11.2 khz <1> fan 2 filter en read/write this bit enables fan filtering for fan 2. <2> fan 1 filter en read/write this bit enables fan filtering for fan 1. adm1031 rev. 3 | page 33 of 35 | www.onsemi.com table 27. register 024 local temp t min /t range power-on default = 41h bit name r/ w description <7:3> > local temp t min read/write contains the minimum temperature value for automatic fan speed control based on local temperature readings. t min can be programmed to positive values only in 4c increments. default is 32c. 00000 = 0c 00001 = 4c 00010 = 8c 00011 = 12c | | 01000 = 32c (default) | | | 11110 = 120c 11111 = 124c <2:0> local temp t range read/write this nibble contains the temperature range value for automatic fan speed control based on the local temperature readings. 000 = 5c 001 = 10c (default) 010 = 20c 011 = 40c 100 = 80c table 28. register 025 remote 1 temp t min /t range power-on default = 61h bit name r/ w description <7:3> remote 1 temp t min read/write contains the minimum temperature value for automatic fan speed control based on local temperature readings. t min can be programmed to positive values only in 4c increments. default is 32c. 00000 = 0c 00001 = 4c 00010 = 8c 00011 = 12c | | 01100 = 48c | | | 11110 = 120c 11111 = 124c <2:0> remote 1 temp t range read/write this nibble contains the temperature range value for automatic fan speed control based on the remote 1 temp readings. 000 = 5c 001 = 10c (default) 010 = 20c 011 = 40c 100 = 80c adm1031 rev. 3 | page 34 of 35 | www.onsemi.com table 29. register 026 remote 2 temp t min /t range power-on default = 61h bit name r/ w description <7:3> remote 2 temp t min read/write contains the minimum temperature value for automatic fan speed control based on remote 2 temperature readings. t min can be programmed to positive values only in 4c increments. default is 32c. 00000 = 0c 00001 = 4c 00010 = 8c 00011 = 12c | | 01100 = 48c (default) | | 11110 = 120c 11111 = 124c <2:0> remote 2 temp t range read/write this nibble contains the temperature range value for automatic fan speed control based on the remote 2 temp readings. 000 = 5c 001 = 10c (default) 010 = 20c 011 = 40c 100 = 80c table 30. register 03f therm behavior/revision power-on default = 80h bit name r/ w description <7> therm-to- fan en read/write setting this bit to 1, en ables the fan to run full-speed when therm is asserted low. this allows the system to be run in performance mode. clearing this bit to 0 disables the fan from running full-speed whenever therm is asserted low. this allows the system to run in silent mode. (power-on default = 1). <3:0> revision read only this nibble contains the revision number for the adm1031. table 31. register 00d local temperature offset power-on default = 00h bit name r/ w description <7> sign read/write when this bit is 0, the local offset is adde d to the local temperature reading. when this bit is set to 1, the local offset is subtracted from the local temperature reading. <3:0> local offset read only these four bits are used to add an offset to the local temperature reading. these bits allow an offset value of up to 15c to be added to or subtracted from the temperature reading. table 32. register 00e remote 1 temperature offset power-on default = 00h bit name r/ w description <7> sign read/write when this bit is 0, the remote offset is added to the remote 1 temperature reading. when this bit is set to 1, the remote offset is subtracted from the remote 1 temperature reading. <6.4> unused read/write unused. read back 0. <3:0> remote 1 offset read/write these four bits are used to add an offset to the remote 1 temperature reading. these bits allow an offset value of up to 15c to be added to or subtracted from the temperature reading, depending on the sign bit. table 33. register 00f remote 2 temperature offset power-on default = 00h bit name r/ w description <7> sign read/write when this bit is 0, the remote offset is added to the remote 2 temperature reading. when this bit is set to 1, the remote offset is subtracted from the remote 2 temperature reading. <6.4> unused read/write unused. read back 0. <3:0> remote 2 offset read/write these four bits are used to add an offset to the remote 2 temperature reading. these bits allow an offset value of up to 15c to be added to or subtracted from the temperature reading, depending on the sign bit. adm1031 rev. 3 | page 35 of 35 | www.onsemi.com outline dimensions compliant to jedec standards mo-137-ab 16 9 8 1 pin 1 seating plane 0.010 0.004 0.012 0.008 0.025 bsc 0.010 0.006 0.050 0.016 8 0 coplanarity 0.004 0.065 0.049 0.069 0.053 0.197 0.193 0.189 0.158 0.154 0.150 0.244 0.236 0.228 figure 41. 16-lead shrink small outline package [qsop] (rq-16) dimensions shown in inches ordering guide model temperature range package description package option adm1031arq 0c to +100c 16-lead qsop rq-16 ADM1031ARQ-REEL 0c to +100c 16-lead qsop rq-16 ADM1031ARQ-REEL7 0c to +100c 16-lead qsop rq-16 adm1031arqz 1 0c to +100c 16-lead qsop rq-16 adm1031arqz-reel 1 0c to +100c 16-lead qsop rq-16 adm1031arqz-r7 1 0c to +100c 16-lead qsop rq-16 eval-adm1031eb evaluation board 1 z = pb-free part. on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to make changes witho ut further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any parti cular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without li mitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specif ications can and do vary in different applications and actu al performance may vary over time. all operating parameters, including ?typicals? must be validated for each custom er application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surg ical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized appli cation, buyer shall indemnify and hold scillc and its officers , employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonabl e attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information literature fulfillment: literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone: 303-675-2175 or 800-344-3860 toll free usa/canada fax: 303-675-2176 or 800-344-3867 toll free usa/canada email: orderlit@onsemi.com n. american technical support: 800-282-9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81-3-5773-3850 on semiconductor website: www.onsemi.com order literature: http://www.onsemi.com/orderlit for additional information, please contact your local sales representative |
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